چکیده (انگلیسی):

In modern wireless communication world, the security of
data transfer has been the most challenging task. In embedded
system, AES is the most extensively used cryptographic algorithm in
practice. But its functionality has been disrupted by the DPA attack.
There have been several countermeasures to tackle those attacks, but
this study proposes variably a new measure to defend this DPA
attack. DPA attack is possible due to the power fluctuation
happening due to sequential circuit clocking during the process of
substitute byte in AES encryption in the first round and last round.
Hence to prevent this, the power variation is maintained at a constant
pace throughout the data processing. This is achieved by
incorporating a combinational logic design instead of a sequential
logic circuit in AES. The proposed design is implemented in Vertex
III FPGA device and found even after 17230 power traces the secret
key is not disclosed as the power fluctuations is completely random.
The power consumption when experimented by micro wind software
proves to be constant and the same power (almost) is obtained while
implementing it hardware and no chance of identifying the instant of
data processing is achieved.